CDNLive EMEA offered the engineers and industry experts an platform to connect, share and discover new techniques and methodologies.

It was highlighted that one of the main growth areas for semiconductors is the automotive industry, where the average semiconductor content per vehicle is expected to increase. Other growth drivers will be compute, wireless and consumer electronics.

In system design and verification, Indago Debug Platform, Perspec System verifier, Cadence JasperGold Formal Apps and Protium FPGA rapid prototyping was presented.

Indago™ Debug Platform: Indago™ Debug Platform, a new debugging solution which reduces the time to identify bugs in a design by up to 50 percent compared to traditional signal- or transaction-level debug methods.With its patented root-cause analysis technology, the Indago Debug Platform filters unneeded data to go beyond the source for a single bug to resolve the cause of all related bugs.

With a unified debug platform and the debug apps, the Indago Debug Platform enables multiple engineering specialists from design, testbench, embedded software and protocol verification to operate as a team to resolve SoC bugs. The three debug apps are:

1. Indago Debug Analyzer:  Extends root-cause analysis from etestbench (IEEE 1647) to SystemVerilog (IEEE 1800) and increases performance by up to 10X
2. Indago Embedded Software Debug: Resolves bugs associated with embedded software applications by synchronizing software and hardware source code debug
3. Indago Protocol Debug:  Visualizes advanced protocols such as DDR4, ARM® AMBA® AXI and ACE using Cadence VIP for intuitive debugging

 

Perspec System verifier: Perspec System verifier platform is for use-case  scenario-based software-driven system-on-chip (SoC) verification. Using an intuitive graphical specification of system-level verification scenarios and a definition of the SoC topology and actions, this new verification solution automates system-level coverage-driven test development using constraint-solving technology, delivering up to 10X productivity improvement in SoC verification versus typical manual test development.

Perspec System Verifier delivers increased productivity and SoC quality through several key features, including:

1. A Unified Modeling Language (UML) based view of system-level actions and resources that, combined with powerful solver technology, creates an intuitive view of complex and hard-to-test system-level use-case interactions
2. Solver technology, which automates the generation of portable tests to deliver complete coverage of system-level scenarios based on chip constraints and the scope of the scenarios to verify SoC-level features for functionality, performance and power
3. Tests that run on all pre-silicon verification platforms including simulation, acceleration and emulation, and virtual and FPGA prototyping, which can be further used to validate actual silicon

 

Cadence JasperGold Formal Apps: Cadence JasperGold Apps perform multiple formal-based verification tasks and leverage a common formal verification platform, database and user interface. Cadence JasperGold Apps automate property creation for many common verification tasks, enabling rapid adoption by both design and verification engineers without previous formal experience. All JasperGold Apps leverage the Cadence Jasper Visualize™ graphical visualization and debug technology for fast debugging and a consistent user experience.

Protium FPGA prototyping: The Protium platform reduces prototype bring-up time by up to 70%, shortening the process from months to weeks. The platform supports up to 100 million gates, which is a 4X increase in capacity compared to the first-generation Rapid Prototyping Platform. With a fully automatic software flow, the Protium platform delivers high performance that can be further optimized with user-driven optimizations, essential for early software development. Other Protium features include:

1. Automated memory compilation
2. External bulk memory support
3. RTL name preservation throughout the flow, which minimizes manual FPGA bring-up steps and debug to speed up time to market
4. Unique, easy-to-use debug capabilities, including signal monitoring, force/release signal, internal memory upload/download, probes, and cross FPGA triggering.